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2.5 Gbit/s Retiming Laser Driver GD16571
Preliminary
General Description
The GD16571 is a high performance low power 2.5 Gbit/s Laser Driver with optional on chip retiming of data. The GD16571 is designed to meet and exceed ITU-T STM-16 or SONET OC-48 fiberoptic communication systems requirements. The GD16571 is designed to sink a Modulation Current into the IOUT pin and a Pre-Bias Current into the IPRE pin. The Modulation Current is adjustable up to 70 mA by means of the pin VMOD. The Pre-Bias Current may be adjusted up to 50 mA by means of the VPRE pin. Retiming of the data signal connected to the pins DIN, DINQ is made by means of a DFF clocked by an external clock signal at the data rate fed to the pins CKIN and CKINQ. A Mark-Space monitor is available on the pins MARKP and MARKN. Together with the symmetry adjustment pin (SYM) this may be used to control the mark space ratio of the output signal. The GD16571 is implemented in a Silicon Bipolar process and requires a single +5 V supply or a single -5.2 V supply. The circuit is available in a thermally enhanced 32-pin TQFP plastic package.
Features
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Complies with ITU-T STM-16 and SONET OC-48 standards. Intended for driving a 25 W load, e.g. a laser diode with 25 W input impedance. Clocked or non-clocked operation. Large modulation current adjustment range from 5 mA to 70 mA. Output voltage over / under shoot less than 2 % respectively 5 %. Rise / fall times less than 100 ps. Laser diode pre-bias adjustable up to 50 mA. Mark-Space monitor. Symmetry adjustment. Internal 50 W termination of data and clock inputs. Operates up to 3.5 Gbit/s. Power dissipation: 0.38 W. Excluding Modulation Current and Pre-bias Current. Silicon Bipolar process. 32 pin thermally enhanced TQFP plastic package.
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VADJEF
VMOD
VADJBUF
VPRE
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Modulation Current Control CKSEL DIN DINQ
50 50
Pre-Bias Current Control
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IPRE
Input Buffer
Output Driver
VDD VDDR VDDCONT IOUT IOUTN VEE VEEP VEEB VEER MARKP MARKN
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MUX
D
Q
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DINT CKIN CKINQ
50 50
Input Buffer
Mark/Space Monitor
SYM
CKINT
Applications
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Tele Communication: - SDH STM-16 - SONET OC-48 Datacom up to 3.125 Gbit/s. Electro Absorption laser driver. Direct Modulation laser driver.
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Data Sheet Rev.: 10
Functional Details
GD16571 is a 2.5 Gbit/s laser driver with an optional retiming of the data signal. It is capable of driving high power laser diodes, typically having input impedance of 25 W, at a maximum modulation current of 70 mA and a maximum pre-bias current of 50 mA. Data (DIN, DINQ) is input to GD16571 and retimed within a DFF clocked by an external clock (CKIN, CKINQ). Optionally the retiming may be bypassed controlled by a select pin (CKSEL). Both the differential data (DIN, DINQ) and clock inputs (CKIN, CKINQ) are internally terminated to 50 W. Termination is made with a 50 W resistor from the two differential inputs to a common pin called DINT and CKINT respectively. The input sensitivity when driven with a single ended signal is better than 150 mV on both clock and data inputs. The output pin (IOUT) is an open collector output designed for driving external loads with 25 W characteristic impedance. Because of the nature of an open collector the output therefore may be regarded as a current switch, with infinite output impedance. The characteristic impedance through the package is approximately 25 W. Optimum performance of GD16571 therefore is achieved if the output is terminated into a 25 W impedance. The output modulation current is controlled by the pin VMOD and can be controlled in the range from 0 mA to 70 mA, however the specifications is only valid in the range from 5 mA to 70 mA. The output voltage swing across the external load may be varied accordingly. The modulation current control on pin VMOD is implemented as a current mirror and therefore sinks a current proportional to the modulation current. The current sink into the VMOD pin is approximately 3/80 of the modulation current. Two additional pins (VADJBUF and VADJEF) are available in order to optimise the performance of the output signal quality, specifically with respect to overshoot and undershoot. Typically best performance is obtained if these pins are connected to VMOD. The pre-bias current is controlled by the pin VPRE and can be controlled from 0 mA to 50 mA. The pre-bias current control on pin VPRE is implemented as a current mirror and therefore sinks a current proportional to the pre-bias current. The current sink into the VPRE pin is approximately 3/500 of the pre-bias current. An important parameter for laser drivers is voltage overshoot on the output pin (IOUT), because it determines the extinction ratio. GD16571 has been designed with special emphasis on achieving a very small voltage overshoot. For
Control Voltage from Modulation Current Control System Control Voltage from Pre-Bias Current Control System
GD16571 the voltage overshoot is less than 2 % across the full modulation current range, when driving a 25 W load. Similarly the voltage undershoot is less than 5 %. A mark-space monitor is provided through the pins MARKP and MARKN. These may be connected as shown in the application diagram below, with a capacitor across the two outputs and a comparator (or Op-amp) to determine the mark density. Symmetry input (SYM) is available which may be used to control the mark-space ratio.
AC Coupled Output
When DC coupled the output swing will be limited by IOUT output voltage specified to -2 V. For maximum output voltage swing the output should be AC coupled.
VDD L1 220uH L3 220uH VDD
L2
L4
L1 and L3 = Siemens Chip Inductors (B82432A1224K). L2 and L4 = Siemens ferrite cores B64290-A36-X33 with 8 turns of 0.22mm Cu-Wire.
100nF 100nF 25W VDD
IOUT IOUTN
Figure 2. AC Coupled Output
VMOD / 20
VPRE / 16
Laser Diode Equivalent 25 W Input Impedance
Modulation Current Control
Pre-Bias Current Control
IPRE / 19
VDD
VDD
25
Differential or Single-ended Data Signal
50 50
DIN / 27 DINQ / 26
50 50
Input Buffer
Output Driver IOUT / 13, 14 IOUTN / 11, 12
L C C 25 L VDD 25
100n 50 50
DINT / 28
Differential or Single-ended Clock Signal
CKIN / 31 CKINQ / 32
50 50
Input Buffer
Mark/Space Monitor MARKP / 7 MARKN / 6
VDD 100n
100n
CKINT / 30
VEEP / 18
+
Ref.
Negative Supply
Figure 1. Application Diagram Data Sheet Rev.: 10 GD16571 Page 2 of 7
Pin List
Mnemonic: DIN DINQ DINT CKIN CKINQ CKINT IOUT IOUTN IPRE VMOD Pin No.: 27 26 28 31 32 30 13, 14 11, 12 19 20 Pin Type: AC IN ANL IN AC IN ANL IN OPEN COLLECTOR OPEN COLLECTOR ANL IN Description: Data inputs. Internally terminated in 50 W to DINT. Internally biased to -1.3 V Termination voltage for DIN and DINQ. Clock inputs. Internally terminated in 50 W to CKINT. Internally biased to -1.3 V. Termination voltage for CKIN and CKINQ. Laser Driver Output (2.5 Gbit/s). IOUT and IOUTN sink a modulation current, which is controlled by the pin VMOD. The current into IOUT is high when data is high on DIN. Pre-bias current output. IPRE sinks a current, which is controlled by the pin VPRE. Modulation current control input. The control system is made as a current mirror. VMOD sinks a current proportional to the modulation current. This current is approximately 3/80 times "The modulation current". Pre-bias current control input. The control system is made as a current mirror. VPRE sinks a current proportional to the pre-bias current. This current is approximately 3/500 times "The pre-bias current". When CKSEL is low data is retimed. Otherwise data is bypassed the retiming. SYM controls the mark-space ratio of the output. Decreasing the voltage of the SYM pin decreases the pulse width of a current high into the IOUT pin. Mark-space monitor outputs. High impedance CML outputs. The output voltage of the MARKP pin is the same as the voltage on the DIN input. Pins used to optimise the performance of the output in terms of overshoot and undershoot. Typically optimum performance will be achieved when shorted to VMOD. Ground pins for laser driver part. Ground pin for modulation current control system. Ground pin for retiming part. Negative supply pins for laser driver part. Negative supply pin for output driver. Negative supply pin for pre-bias circuitry. Negative supply pin for retiming part. Not Connected. Connected to VEE.
VPRE
16
ANL IN
CKSEL SYM
1 24
ECL IN ANL IN
MARKP MARKN VADJBUF VADJEF VDD VDDCONT VDDR VEE VEEP VEEB VEER NC Heat sink
7 6 22 21 2, 4, 10, 15 3 29 5, 8, 23 18 17 25 9 Package back
ANL OUT
ANL IN
PWR PWR PWR PWR PWR PWR PWR
Data Sheet Rev.: 10
GD16571
Page 3 of 7
Package Pinout
CKINQ
32
CKINT
30
VDDR
VEER
DINQ
CKIN
31
DINT
28
DIN
27
25
26
29
CKSEL VDD VDDCONT VDD VEE MARKN MARKP VEE
1 2 3 4 5 6 7 8
24 23 22 21 20 19 18 17
SYM VEE VADJBUF VADJEF VMOD IPRE VEEP VEEB
16
15
14
13
12
10
11
9
VPRE
VDD
IOUT
IOUT
IOUTN
IOUTN
VDD
NC
Figure 3. Package 32 TQFP, Top View
Maximum Ratings
These are the limits beyond which the component may be damaged. All voltages in table are referred to VDD. All currents in table are defined positive out of the pin. Symbol: VEE VO VI II AC IN II VMOD II VPRE TO TS Note 1: Characteristic: Power Supply Applied Voltage (All Outputs) Applied Voltage (All Inputs) Input Current (AC IN) Input Current (VMOD) Input Current (VPRE, VADJBUF and VADJEF) Operating Temperature Storage Temperature Voltage and/or current should be externally limited to specified range. Note 1 Base Conditions: MIN.: -6 VEE -0.5 VEE -0.5 -1 -4 -1 -55 -65 TYP.: MAX.: 0 2 0.5 1 1 1 +125 +165 UNIT: V V V mA mA mA C C
Data Sheet Rev.: 10
GD16571
Page 4 of 7
DC Characteristics
TCASE = -40 C to 85 C, appropriate heat sinking may be required. All voltages in table are referred to VDD. All currents in table are defined positive out of the pin. Symbol: VEE IEE PDISS Characteristic: Power Supply Negative Supply Current Power Dissipation IOUT = 0 A VEE = -5.0 V, IOUT = 0 A, IPRE = 0 A 150 VEE -4 VEE -1 VEE -1 VEE -1 -2.0 4.0 -2.0 -50 Note 1 Note 1,2 Note 1,3 -2.0 -70 -3 0 1 0 Conditions: MIN.: -5.5 TYP.: -5.2 75 0.38 0.5 MAX.: -4.7 UNIT: V mA W
Vpp AN IN V VMOD I VMOD VIN NN ISINK NN VIN SYM ILEAK SYM VIN CKSEL ILEAK CKSEL VLO MARK RO MARK VO IPRE I IPRE VO IOUT IMod,HI IOUT IMod,LO IOUT Note 1: Note 2: Note 3:
Peak-peak Voltage when Input is Driven Single VVTH= -1.3 V ended. Voltage Range for VMOD Sink Current into Pin VMOD Input Voltage Range for VPRE, VADJBUF, VADJEF and SYM Sink Current into pin VPRE, VADJBUF, VADJEF and SYM Input Voltage Range for SYM Leakage Current for CKSEL Input Voltage Range for CKSEL Leakage Current for SYM Low Output Voltage for Mark-Space Monitor Output Impedance for Mark-Space Monitor IPRE Output Voltage IPRE Current IOUT Output Voltage IOUT High Modulation Current IOUT Low Modulation Current
800 VDD 0 VDD 0 VDD 1 VDD 1
mV V mA V mA V mA V mA V kW V mA V mA mA
RLOAD = 25 W to VDD connected to pin IOUT. Sink current is controlled by the VMOD pin, and may be adjusted in the range as specified. Notice that high modulation current means that the output voltage level is low. The AC parameters are only specified in the range from -70 mA to -5 mA. However at TCASE = 0 C to 70 C AC parameters are specified from -80 mA to -5 mA. This is a leakage current. Max leakage current is present at max modulation current (i.e. at 70 mA modulation current). The leakage current decreases for smaller leakage currents.
Data Sheet Rev.: 10
GD16571
Page 5 of 7
AC Characteristics
TCASE = -40 C to 85 C, appropriate heat sinking may be required. Symbol: fMAX OUT Jpp OUT tRISE OUT tFALL OUT tPM tS tH DCROSS_OVER Note 1: Characteristic: Data Output Frequency Added Output Jitter Output Rise Time Output Fall Time Phase Margin Clock to Data Data Set-up Time Data Hold Time Output Cross Over Control Range Note 1 Note 1 Note 1 Note 1 300 60 20 30 30 5 Conditions: MIN.: 2500 20 100 100 TYP.: MAX.: UNIT: Mbit/s ps ps ps ps ps ps %
RLOAD = 25 W to VDD connected to pin IOUT. ILD = 70 mA. Rise/Fall times at 20 - 80 % of HI/LO voltage levels.
Package Outline
Figure 4. Package 32 pin. All dimensions are in mm.
Data Sheet Rev.: 10
GD16571
Page 6 of 7
Device Marking
GD16571 <1> - <2> - <3> <4> - YYWW
Pin 1 - Mark
<1> = Wafer ID <2> = Design ID <3> = Wafer Lot# <4> = Assembly Lot#
Figure 5. Device Marking, Top View.
Ordering Information
To order, please specify as shown below: Product Name: Intel Order Number: Package Type: 32L TQFP EDQUAD Temperature Range: -40..85 C
GD16571-32BA
FAGD1657132BA
MM#: 836125
GD16571, Data Sheet Rev.: 10 - Date: 24 July 2001
an Intel company
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The information herein is assumed to be reliable. GIGA assumes no responsibility for the use of this information, and all such information shall be at the users own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. GIGA does not authorise or warrant any GIGA Product for use in life support devices and/or systems.
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Copyright (c) 2001 GIGA ApS An Intel company All rights reserved

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